SH7205 Datasheet, PDF (762/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
• Four types of interrupts: Transmit-FIFO-data-empty interrupt, break interrupt, receive-FIFO-
data-full interrupt, and receive-error interrupts are requested independently.
• When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving
power.
• In asynchronous mode, on-chip modem control functions (RTS and CTS) (only channel 0).
• The quantity of data in the transmit and receive FIFO data registers and the number of receive
errors of the receive data in the receive FIFO data register can be ascertained.
• A time-out error (DR) can be detected when receiving in asynchronous mode.
• In asynchronous mode, the base clock frequency can be either 16 or 8 times the bit rate.
• When an internal clock is selected as a clock source and the SCK pin is used as an input pin in
asynchronous mode, either normal mode or double-speed mode can be selected for the baud
rate generator.
Rev. 1.00 Mar. 25, 2008 Page 730 of 1868
REJ09B0372-0100