SH7205 Datasheet, PDF (1192/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
(2) D0FIFOSEL, D1FIFOSEL
Bit: 15 14 13 12 11 10
RCNT REW DCLRM DREQE MBW[1:0]
Initial value: 0
0
-
R/W: R/W R/W* R
-
0
0
R R/W R/W
9
8
7
— BIGEND —
-
0
-
R R/W R
6
5
4
3
2
1
0
—
—
—
CURPIPE[3:0]
-
-
-
0
0
0
0
R R/W R R/W R/W R/W R/W
Initial
Bit
Bit Name
Value R/W Description
15
RCNT
0
R/W Read Count Mode
Specifies the received data reading mode for the
DTLN bits in DnFIFOCTR.
If this bit is cleared to 0, the DTLN bits in
DnFIFOCTR are cleared when all the received data
in the FIFO buffer that is assigned to the pipe
specified by the CURPOPE bits have been read (in
double buffer mode, the DTLN bit value is cleared
when all the data in a single plane has been read).
If this bit is set to 1, the value in the DTLN bits is
decremented every time the received data is read
from the FIFO buffer that is assigned to the specified
pipe.
0: The DTLN bit is cleared when all of the received
data has been read.
1: The DTLN bit is decremented every time the
received data is read.
Note: When accessing DnFIFO with the BFRE bit set
to 1, set this bit to 0.
Rev. 1.00 Mar. 25, 2008 Page 1160 of 1868
REJ09B0372-0100