SH7205 Datasheet, PDF (188/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Exception Handling
6.9 Stack Status after Exception Handling Ends
The status of the stack after exception handling ends is as shown in table 6.11.
Table 6.11 Stack Status after Exception Handling Ends
Exception Type
Address error
Stack Status
SP
Address of instruction
after executed instruction
SR
32 bits
32 bits
Interrupt
SP
Address of instruction
after executed instruction
SR
32 bits
32 bits
Sleep error
SP
Address of instruction
after executed instruction
SR
32 bits
32 bits
FPU exception
SP
Address of instruction
after executed instruction
SR
32 bits
32 bits
Register bank error (overflow)
SP
Address of instruction
after executed instruction
SR
32 bits
32 bits
Register bank error (underflow)
SP
Start address of relevant
RESBANK instruction
SR
32 bits
32 bits
Rev. 1.00 Mar. 25, 2008 Page 156 of 1868
REJ09B0372-0100