SH7205 Datasheet, PDF (169/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Exception Handling
6.1.2 Exception Handling Operations
Exception sources are detected and their corresponding processing is started with the timing
shown in table 6.2.
Table 6.2 Timing of Exception Source Detection and Start of Exception Handling
Exception Source
Timing of Source Detection and Start of Handling
Reset
Power-on reset Starts on a low-to-high transition on the RES pin, when the H-UDI
reset negate command is set after the H-UDI reset assert
command has been set, or when the WDT overflows.
Manual reset Starts on a low-to-high transition on the MRES pin or when the
WDT overflows.
Address error
Interrupts
Detected during decoding of an instruction and the handling starts
when the execution of the previous instruction is completed.
Register bank Bank underflow Starts upon an attempt to execute a RESBANK instruction when
error
saving to register bank has not been performed.
Bank overflow
In the state where saving has been performed to all register bank
areas, the handling starts when acceptance of register bank
overflow exception has been set by the interrupt controller (the
BOVE bit in IBNR of the INTC is 1) and an interrupt that uses a
register bank has occurred and been accepted by the CPU.
Sleep error
Starts when the SLEEP instruction is executed by CPU0 when the
sleep error enable bit (SLPERE) of standby control register 1
(STBCR1) is 1. For STBCR1, see section 30, Power-Down
Modes.
Instructions Trap instruction Starts on the execution of a TRAPA instruction.
General illegal
instructions
Starts from the decoding of an undefined code placed anywhere
except immediately after a delayed branch instruction (delay slot)
(including an FPU instruction or FPU-related CPU instruction in
FPU module standby state).
Slot illegal
instructions
Starts from the decoding of an undefined code, an instruction that
rewrites the PC, a 32-bit instruction, the RESBANK instruction,
the DIVS instruction, or the DIVU instruction placed directly after a
delayed branch instruction (delay slot) (including an FPU
instruction or FPU-related CPU instruction in FPU module
standby state).
Integer division Starts upon detection of division-by-zero exception or overflow
exception
caused by division of the negative maximum value (H'80000000)
by −1.
Rev. 1.00 Mar. 25, 2008 Page 137 of 1868
REJ09B0372-0100