SH7205 Datasheet, PDF (1296/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Bit
DVST
CTRT
BEMP
Interrupt Name Cause of Interrupt
Function That
Generates the Related
Interrupt
Status
Device state
transition
interrupt
When a device state transition is
detected
• A USB bus reset detected
Function
DVSQ
• The suspend state detected
• Set address request received
• Set configuration request received
Control transfer When a stage transition is detected in
stage transition control transfer
interrupt
• Setup stage completed
Function
CTSQ
• Control write transfer status stage
transition
• Control read transfer status stage
transition
• Control transfer completed
• A control transfer sequence error
occurred
Buffer empty
interrupt
• When transmission of all of the
data in the buffer memory has
been completed
Host,
Function
PIPEBEMP
• When an excessive maximum
packet size error has been
detected
Rev. 1.00 Mar. 25, 2008 Page 1264 of 1868
REJ09B0372-0100