SH7205 Datasheet, PDF (360/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
CKIO
Single read
SDRAM command
ACT WR PRA
Data bus
d0
ACT: Row and bank activation command
WR: Write command
PRA: Precharge-all-banks command
Figure 10.21 Single Write Timing Example (Shortest Timing Settings)
(10) Mode Register Setting
Writing to the SDRAMm mode register (SDmMOD) causes mode register set and extended mode
register set commands to be issued to SDRAM for individual channels. Settings the SDRAMm
mode register (SDmMOD) should be made separately for each channel.
Figure 10.22 shows the operation timing for mode register setting.
CKIO
Mode register
setting cycle
Extended mode register
setting cycle
SDRAM command
MRS DSL DSL
EMRS DSL DSL
3 cycles (fixed)
3 cycles (fixed)
DSL: Deselect command
MRS: Mode register set command
EMRS: Extended mode register set command
Figure 10.22 Operation Timing for Mode Register Setting
Rev. 1.00 Mar. 25, 2008 Page 328 of 1868
REJ09B0372-0100