SH7205 Datasheet, PDF (1463/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
In this case, the integer part (10 bits) of Psh will be in H1PHS_INTGR and the fractional part (12
bits) of Psh will be in H1PHS_DCML. If there is to be no resizing or the magnification is to
remain the same (resizing by a factor of one), set Psh = 0.
The source-side starting phase (Psv) can be calculated by using the following equation:
Psv = Cv × (number of pixels to that where resizing starts) + (initial phase at starting pixel
× 4096)
In this case, the integer part (9 bits) of Psv will be in V1PHS_INTGR and the fractional part (12
bits) of Psv will be in V1PHS_DCML. If there is to be no resizing or the magnification is to
remain the same (resizing by a factor of one), set Psv = 0.
• Range of settings for full resizing
Since this is full resizing, the integer part (V1PHS_INTGR) is always 0.
Enlargement: V1PHS_INTGR = H'000, V1PHS_DCML = H'000 to H'(VDLT_DCML – 1)
Reduction: V1PHS_INTGR = H'000, V1PHS_DCML = H'000 to H'FFF
• Range of settings for partial resizing
Set the integer and fractional parts for correspondence with the pixels at the top-edge of the
area for partial resizing.
The starting phase is used to vary the proportion of mixing for the two source pixels used as a
reference for bilinear filtering in resizing. This can be used to eliminate the omission of pixels in
halving of the size (reduction by a factor of two) and so on. However, too large an initial phase
can lead to a mismatch of colors at the left edge of the destination. For these reasons, the
following limitations apply to settings for the starting phase in resizing.
Limitations:
Always set the integer components of the starting phase (the H1PHS_INTGR and
V1PHS_INTGR bits) to zero.
Set the fractional components of the starting phase (the H1PHS_DCML and V1PHS_DCML
bits) within the ranges given below:
 Resizing for enlargement: H1PHS_DCML and V1PHS_DCML bits = H'000 to H'
(VDLT_DCML – 1)
 Resizing for reduction: H1PHS_DCML and V1PHS_DCML bits = H'000 to H'FFF
Rev. 1.00 Mar. 25, 2008 Page 1431 of 1868
REJ09B0372-0100