SH7205 Datasheet, PDF (1146/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
(2) 4-Symbol ECC Operation
Figure 23.18 shows a flowchart of the operation when the 4-symbol ECC circuit is used. Setting
the 4ECCEN bit in FLCMNCR enables the 4-symbol ECC circuit and ECC is generated and
output for each sector. If the 4ECCCORRECT bit in FLCMNCR is also set to 1, information
necessary for correction pattern generation is accumulated in the 4-symbol ECC circuit.
In the case when the FLCTL is reading data from flash memory by continuous sector access, the
reading operation stops when an error-containing sector has been read regardless of the number of
remaining sectors. After reading of the error-containing sector has ended, generation of error
correction pattern is started by setting the FL4ECCCR register. If the sector contains five or more
errors, that sector is regarded as uncorrectable. Note that a sector may be uncorrectable for some
error patterns even if it contains four or less errors. In such a case, invalid data are placed in the
FL4ECCRES1 to FL4ECCRES4 registers.
Rev. 1.00 Mar. 25, 2008 Page 1114 of 1868
REJ09B0372-0100