SH7205 Datasheet, PDF (424/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.8 DMA Control Register A (DMCNTAn)
DMCNTAn is used to select transfer modes, transfer conditions, and DMA sources and control
various reload functions.
Bit: 31
-
Initial value: 0
R/W: R
Bit: 15
-
Initial value: 0
R/W: R
30 29 28 27
-
MDSEL[1:0]
-
0
0
0
0
R R/W R/W R
26 25 24 23
-
DSEL[1:0]
-
0
0
0
0
R R/W R/W R
14 13 12 11 10 9
8
7
-
-
- 2DRLOD BRLOD SRLOD DRLOD -
0
0
0
0
0
0
0
0
R
R
R
R R/W R/W R/W R
22 21 20 19 18 17 16
-
-
-
-
-
STRG[1:0]
0
0
0
0
0
0
0
R
R
R
R
R R/W R/W
6
5
4
3
2
1
0
-
DCTG[5:0]
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W
Bit
31, 30
Initial
Bit Name Value

All 0
29, 28 MDSEL 00
[1:0]
27, 26 
All 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W DMA Transfer Mode Select
These bits are used to set DMA transfer mode. Setting these
bits to 00 selects cycle-stealing transfer mode. Setting these
bits to 01 selects pipelined transfer mode. Do not set these
bits to 10 or 11. Operation is not guaranteed if these settings
are made (for details, see section 11.4.1, DMA Transfer
Mode).
00: Cycle-stealing transfer
01: Piepelined transfer
10: Setting prohibited
11: Setting prohibited
Note: If the source or destination is an SDRAM device when
pipelined transfer mode (MDSE L = 01) is selected,
non-stop transfer (DSEL = 11) cannot be set.
R Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 25, 2008 Page 392 of 1868
REJ09B0372-0100