SH7205 Datasheet, PDF (619/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
• Example of Procedure for Setting Output Waveform Control at Synchronous Counter Clearing
in Complementary PWM Mode
An example of the procedure for setting output waveform control at synchronous counter
clearing in complementary PWM mode is shown in figure 12.57.
Output waveform control at
synchronous counter clearing
Stop count operation
[1]
Set TWCR and
complementary PWM mode ^[2]
Start count operation
[3]
[1] Clear bits CST3 and CST4 in the timer
start register (TSTR) to 0, and halt timer
counter (TCNT) operation. Perform
TWCR setting while TCNT_3 and
TCNT_4 are stopped.
[2] Read bit WRE in TWCR and then write 1
to it to suppress initial value output at
counter clearing.
[3] Set bits CST3 and CST4 in TSTR to 1 to
start count operation.
Output waveform control at
synchronous counter clearing
Figure 12.57 Example of Procedure for Setting Output Waveform Control at Synchronous
Counter Clearing in Complementary PWM Mode
Rev. 1.00 Mar. 25, 2008 Page 587 of 1868
REJ09B0372-0100