SH7205 Datasheet, PDF (1148/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
(3) 4-Symbol ECC Error Correction Pattern Generation
The 4-symbol ECC circuit of the FLCTL can generate error correction patterns by hardware. The
original data can be restored by using the error correction patterns. Since the hardware processing
only covers generation of error correction patterns, processing for data restoration must be
provided by software.
The error correction patterns are output in the following format. The bits in a correction pattern at
error bit positions are set to 1, so the original data is restored by taking EOR of error data and error
correction pattern.
• Example 1
Original data:
B'00000000
Erroneous data:
B'11111111
Correction pattern: B'0011111111 (higher two bits are unnecessary data)
Recovered data:
B'00000000
(EOR of error pattern and correction pattern)
• Example 2
Original data:
B'10101010
Erroneous data:
B'01010101
Correction pattern: B'0011111111 (higher two bits are unnecessary data)
Recovered data:
B'10101010
(EOR of error pattern and correction pattern)
• Example 3
Original data:
B'11110000
Erroneous data:
B'00000000
Correction pattern: B'0011110000 (higher two bits are unnecessary data)
Recovered data:
B'11110000
(EOR of error pattern and correction pattern)
Rev. 1.00 Mar. 25, 2008 Page 1116 of 1868
REJ09B0372-0100