SH7205 Datasheet, PDF (1246/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Bit
Bit Name
13
CSCLR
12
CSSTS
Initial
Value
0
0
R/W Description
R*¹/W*² C-Split Status Clear for Split Transaction
When the host controller function is selected,
setting this bit to 1 clears the CSSTS bit to 0.
This bit should be set to 1 to restart the next
transfer with S-Split forcibly in transfer using the
split transaction. However, in normal split
transactions, the CSSTS bit is automatically cleared
to 0 upon completion of the C-Split; therefore,
processing for clearing the CSSTS bit is not
necessary.
0: No effect
1: Clears the CSSTS bit to 0.
Note: Controlling the CSSTS bit through this bit
must be done while UACT is 0 and thus
communication is halted or while no transfer
is being performed with bus disconnection
detected.
Setting this bit to 1 while CSSTS is 0 has no
effect.
R
COMPLETE SPLIT (C-Split) Status of Split
Transaction
Indicates the C-Split status of the split transaction
when the host controller function is selected.
This bit is set to 1 upon start of the C-Split and
cleared to 0 upon detection of C-Split completion.
0: START-SPLIT (S-Split) transaction being
processed or processing of a device not using
split transaction is in progress
1: C-Split transaction being processed
Rev. 1.00 Mar. 25, 2008 Page 1214 of 1868
REJ09B0372-0100