SH7205 Datasheet, PDF (345/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
(4) Access Type and Data Alignment
(a) 32-Bit Bus Channel
If a 32-bit bus is selected by the external bus width select bits in the CSn control register, A25 to
A2 are enabled as address signals for longword units and A1 and A0 are disabled (fixed at low
level). Table 10.6 lists the data alignment corresponding to byte addresses for different data sizes.
If byte strobe mode (WRMOD = 0) is selected, the WE3 to WE0 signals indicate the bits to be
accessed. For read access, however, all bits are access targets regardless of the state of the WE3 to
WE0 signals.
If one-write strobe mode (WRMOD = 1) is selected, the BC3 to BC0 signals indicate access
targets for both read and write accesses. For write access, the write strobe signal WE is also
asserted.
Table 10.6 Data Alignment (32-Bit Bus Channel)
Data Size
Byte Address
DATA
(Lower 2 Bits) [31:24] [23:16] [15:8] [7:0] [3]
WE/BC
[2] [1] [0]
Byte
0
O
×
×
×
L
H
H
H
1
×
O
×
×
H
L
H
H
2
×
×
O
×
H
H
L
H
3
×
×
×
O
H
H
H
L
Word
0
O
O
×
×
L
L
H
H
2
×
×
O
O
H
H
L
L
Longword
0
O
O
O
O
L
L
L
L
Note: The valid bits on the data bus for each data size are indicated by circles (O).
Crosses (×) indicate bus data bits that are undefined.
Rev. 1.00 Mar. 25, 2008 Page 313 of 1868
REJ09B0372-0100