SH7205 Datasheet, PDF (1426/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
(6) Relations between the Sync Signals for the Output Block and the Individual Clock
Signals
(a) With an externally mounted video-decoder LSI
In cases where a moving-picture input is being supplied to the system, set the MVON bit in the
MGR_MIXMODE register to 1. Then, the free-running HSYNC_dck (internal signal) is generated
from DCLKIN and VSYNC_dck (internal signal) is created from the VIVSYNC signal. After that,
the CSYNC signal is composed from the two signals, i.e. HSYNC_dck and VSYNC_dck.
When the system includes an external video decoder LSI but this is not supplying the moving-
picture input with a signal, set the MVON bit in MGR_MIXMODE register to 0. In this case, the
free-running HSYNC_dck generated from DCLKIN is counted and the hardware itself produces
the VSYNC_dck: the CSYNC signal is again composed from the HSYNC_dck and the
VSYNC_dck.
(b) Without externally mounted video decoder LSI
In cases where there is no external video-decoder LSI to supply the system with a moving picture
input, set the MVON bit in MGR_MIXMODE to 0. In this case, since only the free-running
HSYNC_dck generated from DCLKIN is available, the hardware automatically produces the
VSYNC_dck signal by counting cycles of HSYNC_dck, and then composes the CSYNC signal
from HSYNC_dck and VSYNC_dck.
References:
• The image data from the output block, (the image data composed from the moving-picture and
graphics data), and the CSYNC signal are output in synchronization with rising edges of the
externally input DCLKIN signal.
• Timing with which the graphics data are read from the SE buffer is controlled by the
HSYNC_dck and VSYNC_dck signals, and the MGR_SESET register (timing is not
controlled by the VICLK system).
• For externally input moving pictures, the valid number of pixels horizontally is controlled by
the VICLKENB signal and the valid number of lines is set by the VLDPV bits in the
MGR_MIXVS register.
• Externally input moving pictures specified valid area are resized and then written to the data
buffer. Reading of the data from the buffer is controlled by signals HSYNC_dck, and
VSYNC_dck, and register MGR_MIXxx.
Rev. 1.00 Mar. 25, 2008 Page 1394 of 1868
REJ09B0372-0100