SH7205 Datasheet, PDF (754/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 15 Realtime Clock (RTC)
15.3.18 RTC Control Register 3 (RCR3)
When the ENB bit is set to 1, RCR3 performs a comparison with the RYRCNT. From among
RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm
register comparison is performed only on those with ENB bits set to 1, and if each of those
coincides, an alarm flag of RCR1 is set to 1.
BIt: 7
6
5
4
3
2
1
0
ENB -
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R R R R R R R
Initial
Bit Bit Name Value
7
ENB
0
6 to 0 
All 0
R/W Description
R/W When this bit is set to 1, comparison of the year alarm
register (RYRAR) and the year counter (RYRCNT) is
performed.
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 25, 2008 Page 722 of 1868
REJ09B0372-0100