SH7205 Datasheet, PDF (705/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 13 Compare Match Timer (CMT)
13.2.1 Compare Match Timer Start Register (CMSTR)
CMSTR is a 16-bit register that selects whether compare match counter (CMCNT) operates or is
stopped.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
STR1/ STR0/
STR3 STR2
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W R/W
Bit
15 to 2
Bit Name

Initial
Value
All 0
1
STR1/STR3 0
0
STR0/STR2 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Count Start 1/3
Specifies whether compare match counter_1/3 operates
or is stopped.
0: Counting by CMCNT_1/CMCNT_3 is stopped
1: Counting by CMCNT_1/CMCNT_3 is started
R/W Count Start 0/2
Specifies whether compare match counter_0/2 operates
or is stopped.
0: Counting by CMCNT_0/CMCNT_2 is stopped
1: Counting by CMCNT_0/CMCNT_2 is started
Rev. 1.00 Mar. 25, 2008 Page 673 of 1868
REJ09B0372-0100