SH7205 Datasheet, PDF (1401/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
26.3.17 Resize Vertical Starting Phase Register for Blitter (GR_VSPHAS)
The register GR_VSPHAS sets results of the starting position phase computation in the vertical
direction for the blitter resizing.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
V1PHS_DCML
Initial value: -
-
-
-
0
0
00
0
0
0
0
0
0
0
0
R/W: R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
R/W: R
R
R
R
R
R
9
8
7
6
5
4
3
2
1
0
-
V1PHS_INTGR
-
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit name
Initial
Value
R/W Description
31 to 28 
Undefined R Reserved
The read value is undefined. The write value should
always be 0.
27 to 16 V1PHS_DCML H'000
R/W Vertical Starting Position Phase Computation Result
Fractional Part
These bits set the fractional part of the starting-
position phase computation result in the vertical
direction on the source side.
15 to 9 
Undefined R Reserved
The read value is undefined. The write value should
always be 0.
8 to 0 V1PHS_INTGR H'000
R/W Vertical Starting Position Phase Computation Result
Integer Part
These bits set the integer part of the starting-
position phase computation result in the vertical
direction on the source side.
Note: This register must be set before resizing. All bits should be cleared to 0 when resizing is not
performed.
Rev. 1.00 Mar. 25, 2008 Page 1369 of 1868
REJ09B0372-0100