SH7205 Datasheet, PDF (1571/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 29 On-Chip RAM
• Port
On-chip high-speed RAM0 is connected to the CPU0 instruction fetch bus, CPU0 memory
access bus, and on-chip high-speed RAM0 access bus. When CPU0 accesses on-chip high-
speed RAM0 through the address spaces shown in table 29.1, the CPU0 instruction fetch bus
or CPU0 memory access bus is used. When CPU0 accesses on-chip high-speed RAM0 through
the address spaces shown in table 29.2, the on-chip high-speed RAM0 access bus is used.
When CPU1 or DMAC accesses on-chip high-speed RAM0, the on-chip high-speed RAM0
access bus is used in access through the both address spaces shown in table 29.1 and table
29.2.
On-chip high-speed RAM1 is connected to the CPU1 instruction fetch bus, CPU1 memory
access bus, and on-chip high-speed RAM1 access bus. When CPU1 accesses on-chip high-
speed RAM1 through the address space shown in table 29.1, the CPU1 instruction fetch bus or
CPU1 memory access bus is used. When CPU1 accesses on-chip high-speed RAM1 through
the address space shown in table 29.2, the on-chip high-speed RAM1 access bus is used. When
CPU0 or DMAC accesses on-chip high-speed RAM1, the on-chip high-speed RAM1 access
bus is used in access through the both address spaces shown in table 29.1 and table 29.2.
Each page of the on-chip RAM for data retention has one read and write port and is connected
to the peripheral bus.
• Priority
When the same page of the on-chip high-speed RAM is simultaneously accessed from
different buses, the access is controlled based on the priority. The priority order is
on-chip high-speed RAM access bus > memory access bus > instruction fetch bus.
Rev. 1.00 Mar. 25, 2008 Page 1539 of 1868
REJ09B0372-0100