SH7205 Datasheet, PDF (1436/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
1. Write access to the SB buffer is performed for 128 (= 64 × 2) pixels (generating an
INT_SHFUL)
2. If the GR_DOSTAT register is read and the SB buffer is not in a two-banks-full condition,
the data transfer is resumed in units of 64 pixels.
3. If an INT_SHFUL is not generated, the system continues to transfer the remaining 48
pixels, and completes the data transfer process.
In the case of the DC buffer, there will be 256 pixels per bank (or 512 pixels for the two
banks). Since access to the SE buffer can adversely affect display, access by means of a CPU
transfer is not recommended.
Rev. 1.00 Mar. 25, 2008 Page 1404 of 1868
REJ09B0372-0100