SH7205 Datasheet, PDF(722/1904 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

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SH7205 Datasheet, PDF (722/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

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Section 14 Watchdog Timer (WDT)

Initial

Bit

Bit Name Value R/W Description

5

RSTS

*1

R/W Reset Select (only valid for WDT0, reserved bit for

WRCSR1)

(The value of WRCSR0.RSTS determines the reset

type regardless of the WDT in which an overflow

occurs.)

Selects the type of reset when the WTCNT overflows

in watchdog timer mode. In interval timer mode, this

setting is ignored.

0: Power-on reset

1: Manual reset

4 to 0 ï£§

All 1

R

Reserved

These bits are always read as 1. The write value

should always be 1.

Notes: 1. 0 for WRCSR0 and 1 for WRCSR1

2. The LSI is not reset, but WTCNT and WTCSR in WDT are reset.

Rev. 1.00 Mar. 25, 2008 Page 690 of 1868

REJ09B0372-0100

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