SH7205 Datasheet, PDF (528/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Bit
Bit Name Value R/W Description
0
TGFA
0
R/(W)*¹ Input Capture/Output Compare Flag A
Status flag that indicates the occurrence of TGRA input
capture or compare match. Only 0 can be written, for
flag clearing.
[Clearing conditions]
• When DMAC is activated by TGIA interrupt
• When 0 is written to TGFA after reading
TGFA = 1*²
[Setting conditions]
• When TCNT = TGRA and TGRA is functioning as
output compare register
• When TCNT value is transferred to TGRA by input
capture signal and TGRA is functioning as input
capture register
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. When writing to the timer status register (TSR), write 0 to the bit to be cleared after
reading 1. Write 1 to other bits. But 1 is not actually written and the previous value is
held.
Rev. 1.00 Mar. 25, 2008 Page 496 of 1868
REJ09B0372-0100