SH7205 Datasheet, PDF (572/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
• When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously
held in the timer general register is transferred to the buffer register.
This operation is illustrated in figure 12.15.
Input capture
signal
Buffer
register
Timer general
register
TCNT
Figure 12.15 Input Capture Buffer Operation
(1) Example of Buffer Operation Setting Procedure
Figure 12.16 shows an example of the buffer operation setting procedure.
Buffer operation
Select TGR function
[1]
Set buffer operation
[2]
[1] Designate TGR as an input capture register or
output compare register by means of TIOR.
[2] Designate TGR for buffer operation with bits
BFA and BFB in TMDR.
[3] Set the CST bit in TSTR to 1 start the count
operation.
Start count
[3]
<Buffer operation>
Figure 12.16 Example of Buffer Operation Setting Procedure
Rev. 1.00 Mar. 25, 2008 Page 540 of 1868
REJ09B0372-0100