SH7205 Datasheet, PDF (1588/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 30 Power-Down Modes
30.2.10 System Control Register 3 (SYSCR3)
SYSCR3 is an 8-bit readable/writable register that enables or disables access (read/write) from
CPU1 to each page of the high-speed on-chip RAM0. Other descriptions on this register are the
same as SYSCR1.
Note: When writing to this register, see section 30.4, Usage Notes.
30.2.11 System Control Register 4 (SYSCR4)
SYSCR4 is an 8-bit readable/writable register that enables or disables writing from CPU1 to each
page of the high-speed on-chip RAM0. Other descriptions on this register are the same as
SYSCR2.
Note: When writing to this register, see section 30.4, Usage Notes.
30.2.12 System Control Register 5 (SYSCR5)
SYSCR5 is an 8-bit readable/writable register that enables or disables access (read/write) from the
DMAC to each page of the high-speed on-chip RAM0. Other descriptions on this register are the
same as SYSCR1.
Note: When writing to this register, see section 30.4, Usage Notes.
30.2.13 System Control Register 6 (SYSCR6)
SYSCR6 is an 8-bit readable/writable register that enables or disables writing from the DMAC to
each page of the high-speed on-chip RAM0. Other descriptions on this register are the same as
SYSCR2.
Note: When writing to this register, see section 30.4, Usage Notes.
Rev. 1.00 Mar. 25, 2008 Page 1556 of 1868
REJ09B0372-0100