SH7205 Datasheet, PDF (368/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
Figure 10.28 shows the procedure for recovering from deep-power-down mode.
Deep-power-down mode
End deep-power-down mode:
(1) Confirm that all status bits in SDSTR have been cleared to 0
(2) Clear deep-power-down enable bit (DDPD) to 0 by
a program placed in other than the channel of interest
Wait:
Use a timer, etc., to wait for the same duration as the standby time specified
in the power-on sequence (in accordance with the specifications of SDRAM in use)
Initialization sequence:
(1) Set initialization sequence start bit (DINIRQm) to 1 by
a program placed in other than the channel area of interest
(2) Wait for initialization status bit (DINISTm) to be cleared to 0
Mode register setting:
(1) Set the mode register
(2) Set the extended mode register
Start auto-refreshing:
Set DRFEN bit in SDRFCNT1 to 1
Access enabled state:
(EXENB = 1)
Figure 10.28 Procedure for Recovery from Deep-Power-Down Mode
Rev. 1.00 Mar. 25, 2008 Page 336 of 1868
REJ09B0372-0100