SH7205 Datasheet, PDF (1625/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 31 User Debugging Interface (H-UDI)
31.4 Description of the Emulation TAP Controller
To use the emulation TAP controller, enter the emulation TAP controller switching command in
the BSIR register of the boundary scan TAP controller. The emulation TAP controller has the
following registers.
Table 31.5 Register Configuration of the Emulation TAP Controller
Register Name
Bypass register
Instruction register
Abbreviation R/W
SDBPR

BSIR

Initial Value


Address


Access
Size


31.4.1 Bypass Register (SDBPR)
SDBPR is a 1-bit register that cannot be accessed by the CPU. When SDIR is set to BYPASS
mode, SDBPR is connected between H-UDI pins TDI and TDO. The initial value is undefined.
31.4.2 Instruction Register (SDIR)
SDIR is a 16-bit read-only register and initialized by TRST assertion or in the TAP test-logic-reset
state. H-UDI can write to this register regardless of the CPU mode. When a reserved command is
set in this register, the operation is not guaranteed. The initial value is H'EFFD.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TI[7:0]
-
-
-
-
-
-
-
-
Initial value: 1* 1* 1* 0* 1* 1* 1* 1* 1
1
1
1
1
1
0
1
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Note: * The initial value of TI[7:0] is a reserved value, but replace it with a non-reserved value when setting a command.
Bit
15 to 8
Initial
Bit Name Value
R/W
TI[7:0]
11101111* R
Description
Test Instruction
Instruction for the H-UDI is transferred to SDIR as a
serial input from TDI.
For commands, see table 31.6.
Rev. 1.00 Mar. 25, 2008 Page 1593 of 1868
REJ09B0372-0100