SH7205 Datasheet, PDF (334/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
10.5 Operation
10.5.1 Accessing CS Space
(1) Normal Access
Normal read/write operation is used for all bus accesses when page read/write access is disabled
(PRENB = 0, PWENB = 0). Even when page read/write access is enabled (PRENB = 1, PWENB
= 1), normal read/write operation is employed in cases where page access cannot be used. Figure
10.2 shows the basic operation of the external bus control signals for read and write operations in
byte-write strobe mode. Figure 10.3 shows the basic operation of these signals for read and write
operations in one-write strobe mode. In these figures, DACTn is a DMA active output signal. For
details, see section 11, Direct Memory Access Controller (DMAC).
CKIO
A25 to A0
CSn
RD_WR
RD
WEn
Ts Tw1 Tw2 ^{... ... ... ...} Tend Tn1 Tn2 ^... Tnm
(Trd)
Read cycle wait
CS assert wait
CS delay cycle
during read
RD assert wait
D31 to D0
DACTn
Figure 10.2 Basic Bus Timing (Read Operation in Byte-Write Strobe Mode) (a)
Rev. 1.00 Mar. 25, 2008 Page 302 of 1868
REJ09B0372-0100