SH7205 Datasheet, PDF (139/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 4 Multi-Core Processor
Register Name
Abbreviation R/W
Initial
Value
Address
Access
Size
Semaphore register 25
SEMR25
R*²/W H'00
H'FFFC1E64 8
Semaphore register 26
SEMR26
R*²/W H'00
H'FFFC1E68 8
Semaphore register 27
SEMR27
R*²/W H'00
H'FFFC1E6C 8
Semaphore register 28
SEMR28
R*²/W H'00
H'FFFC1E70 8
Semaphore register 29
SEMR29
R*²/W H'00
H'FFFC1E74 8
Semaphore register 30
SEMR30
R*²/W H'00
H'FFFC1E78 8
Semaphore register 31
SEMR31
R*²/W H'00
H'FFFC1E7C 8
Notes: 1. The values H'10111000 and H'50110800, respectively, are read out in response to
reading by CPU0 and CPU1.
2. After being read, the register is cleared to H'00.
4.2.1 CPU ID Register (CPUIDR)
The CPU ID register indicates the CPU number (CPU0 or CPU1).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
ID
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: *
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: *
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W Description
31

*
R
Reserved
A fixed value is read from this bit.
30
ID
*
R
Indicates the CPU number.
“0” is read by CPU0, and “1” is read by CPU1.
29 to 0 
*
R
Reserved
A fixed value is read from these bits.
Note: * Overall values of H'10111000 and H'50110800, respectively, are read out in response
to reading by CPU0 and CPU1.
Rev. 1.00 Mar. 25, 2008 Page 107 of 1868
REJ09B0372-0100