SH7205 Datasheet, PDF (1179/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
6
USBRST
0
R/W PORT1 USB Bus Reset Output
When the host controller function is selected, setting
this bit to 1 causes this module to drive PORT1 to
SE0 to reset the USB bus. Here, this module
performs the reset handshake protocol if the HSE bit
for PORT1 is 1.
This module continues outputting SE0 while
USBRST is 1. Ensure that USBRST stays 1 (= USB
bus reset period) for the time defined by USB
Specification 2.0.
0: USB bus reset signal is not output.
1: USB bus reset signal is output.
Note: Writing 1 to this bit during communication
(UACT = 1) or during the resume process
(RESUME = 1) prevents this module from
starting the USB bus reset process until both
UACT and RESUME become 0.
When the USB bus reset processing has
ended, write 0 to this bit and 1 to the UACT bit
at the same time.
5
RESUME
0
R/W PORT1 Resume Output
When the host controller function is selected, setting
this bit to 1 causes this module to drive PORT1 to
the K-state and perform the resume processing.
This module continues outputting K-state while
RESUME is 1. Ensure that RESUME stays 1 (=
resume period) for the time defined by USB
Specification 2.0.
0: Resume signal is not output.
1: Resume signal is output.
Note: This bit should be set to 1 only in the
suspended state. When the resume
processing has ended, write 0 to this bit and 1
to the UACT bit at the same time.
Rev. 1.00 Mar. 25, 2008 Page 1147 of 1868
REJ09B0372-0100