SH7205 Datasheet, PDF (1616/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 31 User Debugging Interface (H-UDI)
31.2 Input/Output Pins
Table 31.1 Pin Configuration
Pin Name
Symbol I/O Function
H-UDI serial data
input/output clock pin
TCK
Input
Data is serially supplied to the H-UDI from the data
input pin (TDI), and output from the data output pin
(TDO), in synchronization with this clock.
Mode select input pin
H-UDI reset input pin
TMS
TRST
Input
Input
The state of the TAP control circuit is determined
by changing this signal in synchronization with
TCK. The protocol complies with the JTAG
standard (IEEE Std.1149.1).
Input is accepted asynchronously with respect to
TCK, and when low, the H-UDI is reset. TRST must
be low for a period when power is turned on
regardless of using the H-UDI function. See section
31.5.2, Reset Configuration, for more information.
H-UDI serial data input pin TDI
Input Data is transferred to the H-UDI by changing this
signal in synchronization with TCK.
H-UDI serial data output
pin
ASE mode select pin
TDO
Output
Data is read from the H-UDI by reading this pin in
synchronization with TCK. The initial value of the
data output timing is the TCK falling edge, but this
initial value can be changed to the TCK rising edge
by inputting the TDO transition timing switching
command to SDIR. See section 31.5.3, TDO
Output Timing, for more information.
ASEMD* Input
If a low level is input at the ASEMD pin while the
RES pin is asserted, ASE mode is entered; if a high
level is input, product chip mode is entered. In ASE
mode, dedicated emulator function can be used.
The input level at the ASEMD pin should be held
for at least one cycle after RES negation.
Note: * When the emulator is not in use, fix this pin to the high level.
Rev. 1.00 Mar. 25, 2008 Page 1584 of 1868
REJ09B0372-0100