SH7205 Datasheet, PDF (1562/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 28 I/O Ports
28.2.16 Port J Data Register L (PJDRL)
PJDRL is a 16-bit readable/writable register that stores port J data. The PJ12DR to PJ0DR bits
correspond to the PJ12 to PJ0 pins, respectively.
When a pin function is general output, if a value is written to PJDRL, that value is output from the
pin, and if PJDRL is read, the register value is returned regardless of the pin state.
When a pin function is general input, if PJDRL is read, the pin state, not the register value, is
returned directly. If a value is written to PJDRL, although that value is written into PJDRL, it does
not affect the pin state. Table 28.10 summarizes PJDRL read/write operations.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
PJ12 PJ11 PJ10 PJ9 PJ8 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0
DR DR DR DR DR DR DR DR DR DR DR DR DR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
15 to 13 —
All 0
12
PJ12DR 0
11
PJ11DR 0
10
PJ10DR 0
9
PJ9DR 0
8
PJ8DR 0
7
PJ7DR 0
6
PJ6DR 0
5
PJ5DR 0
4
PJ4DR 0
3
PJ3DR 0
2
PJ2DR 0
1
PJ1DR 0
0
PJ0DR 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W See table 28.10.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 1.00 Mar. 25, 2008 Page 1530 of 1868
REJ09B0372-0100