SH7205 Datasheet, PDF (956/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
(2) Reception Using Interrupt-Driven Data Flow Control
Start
Release from reset,
set SSICR configuration bits.
Enable SSI module,
enable data interrupts,
enable error interrupts.
Set TRMD, EN, SCKD, SWSD,
MUEN, DEL, PDTA, SDTA, SPDP,
SWSP, SCKP, SWL, DWL, CHNL.
EN = 1,
UIEN = 1, OIEN = 1,
RIE = 1
Wait for interrupt from SSIF.
Yes
SSIF error interrupt?
No
Read data from receive data register.
Use SSIF status register bits
to realign data
after underflow/overflow.
Yes
Receive more data?
No
Disable SSIF module,
disable data interrupts,
disable error interrupts,
enable idle interrupt.
EN = 0,
UIEN = 0, OIEN = 0,
IIEN = 1, RIE = 0
Wait for idle interrupt
from SSIF module.
End
Figure 19.23 Reception Using Interrupt-Driven Data Flow Control
Rev. 1.00 Mar. 25, 2008 Page 924 of 1868
REJ09B0372-0100