SH7205 Datasheet, PDF (1134/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
23.4 Operation
23.4.1 Access Sequence
The FLCTL performs accesses in several independent stages.
For example, AND-type flash memory programming consists of the following five stages.
• First command issue stage (program setup command)
• Address issue stage (program address)
• Data stage (output)
• Second command issue stage (program start command)
• Status read stage
AND-type flash memory programming access is achieved by executing these five stages
sequentially. An access to flash memory is completed at the end of the final stage (status read
stage).
Program
First
command
Command/
Address
OE
H'10/H'11
SA(1)
CDE
WE
SC
Address
SA(2)
CA(1)
CA(2)
Data
Second
command
Status read
H'40
Data input Program start
Figure 23.2 Programming Operation for AND-Type Flash Memory and Stages
For details on AND-type flash memory read and NAND-type flash memory read/program
operation, see section 23.4.4, Command Access Mode.
Rev. 1.00 Mar. 25, 2008 Page 1102 of 1868
REJ09B0372-0100