SH7205 Datasheet, PDF (1602/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 30 Power-Down Modes
30.3 Operation
30.3.1 Transitions in Power-Down Modes
Figure 30.1 illustrates the state transitions between power-down modes.
Reset
Interrupt request occurs
(CPU0/CPU1 enabled to accept the interrupt)
Dual-processor
NMI interrupt
IRQ interrupt
mode
Interrupt request occurs
(CPU1 enabled to
accept the interrupt)
CPU1 executes
SLEEP instruction
Interrupt request occurs
(CPU0 enabled to
CPU0 executes
accept the interrupt)
SLEEP instruction
with STBY bit clared
Manual reset
Power-on reset
Single-
processor 0 mode
Manual reset
Power-on reset
Single-
processor 1 mode
CPU0 executes
SLEEP instruction
with STBY bit cleared
Interrupt
request occurs
(CPU0 enabled to
accept the interrupt)
CPU1 executes
SLEEP instruction
Interrupt request occurs
(CPU1 enabled to
accept the interrupt)
CPU0 executes
SLEEP instruction
with STBY bit set
and DEEP bit cleared
CPU0 executes
SLEEP instruction
with STBY and DEEP
bits set
Dual-
sleep mode
Software
standby mode
Deep
standby mode
Manual reset
Power-on reset
Manual reset
Power-on reset
NMI interrupt
IRQ interrupt
Manual reset
Power-on reset
Figure 30.1 Transitions of States in Power-Down Modes
Rev. 1.00 Mar. 25, 2008 Page 1570 of 1868
REJ09B0372-0100