SH7205 Datasheet, PDF (337/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
CKIO
A25 to A0
BCn
CSn
RD
WE
D31 to D0
DACTn
Ts Tw1 Tw2 ^{... ... ... ...} Tend Tn1 Tn2 ^... Tnm
Write cycle wait
CS assert wait
CS delay cycle during write
WR assert wait
Write data output wait
Write data output delay cycle
Figure 10.3 Basic Bus Timing (Write Operation in One-Write Strobe Mode) (b)
1. Ts (Internal Bus Access Start)
This is a bus access request cycle initiated by the internal bus master to the external bus as the
target. CSn is always high during this cycle. In the next cycle, A25 to A0, BCn, and the write
data change.
2. Tw1 to Twn (Read Cycle Wait, Write Cycle Wait)
These are the cycles between internal bus access start and the wait end cycle. A duration of
from 0 to 31 clocks may be selected. During this interval the CSn, RD, WEn, and WE signals
are asserted (low level) in accordance with the wait settings. The assert timing can be
controlled using the CS assert wait, RD assert wait, WR assert wait, and write data output wait
bits in CSn control registers 1 and 2. The number of wait cycles can be set to from 0 to 7
clocks, as counted from the cycle following internal bus access start (Ts). The number of
clocks selected must be no greater than the number of read/write cycle wait cycles. The
RD_WR signal operates with the same timing as for the CSn signal.
3. Tend (Wait End Cycle)
This is the final cycle in a series of read cycle wait or write cycle wait cycles. The RD, WEn,
or WE signal is negated (high level) in the next cycle.
Rev. 1.00 Mar. 25, 2008 Page 305 of 1868
REJ09B0372-0100