SH7205 Datasheet, PDF (1344/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 AT Attachment Packet Interface (ATAPI)
(5) Multiword DMA timing register (ATAPI_MULTI_TIMING)
Before accessing an ATAPI device, set the number of machine cycles in the following bits in this
register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
mSDCT
mSDPW
Initial value: ^-
-
-
-
-
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
mMDCT
mMDPW
Initial value: -
-
-
-
-
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 27 

R
Reserved
26 to 21 mSDCT
000000 R/W These bits specify the cycle time for a slave ATAPI
device.
20 to 16 mSDPW 00000
R/W These bits specify the width of the
IDEIORD#/IDEIOWR# pulse for a slave ATAPI device.
15 to 11 

R
Reserved
10 to 5 mMDCT
000000 R/W These bits specify the cycle time for the master ATAPI
device.
4 to 0 mMDPW 00000
R/W These bits specify the width of the
IDEIORD#/IDEIOWR# pulse for the master ATAPI
device.
Note: The prefix mS pertains to slaves, and mM, to the master.
IDEIORD#/
IDEIOWR#
DCT
DPW
DCT: Period setting
DPW: Low-level width setting for the IDEIORD#/IDEIOWR# pulse
Note: The DCT and DPW are determined by their respective register settings × enhanced bus clock period.
Figure 25.3 Multiword DMA Timing Register
Rev. 1.00 Mar. 25, 2008 Page 1312 of 1868
REJ09B0372-0100