SH7205 Datasheet, PDF (1349/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 AT Attachment Packet Interface (ATAPI)
(9) ATAPI control 2 register (ATAPI_CONTROL2)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
WORD
SWAP
IFEN
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W R/W
Bit
31 to 2
1
Bit Name
Initial
Value


WORDSWAP 0
0
IFEN
0
R/W Description
R
Reserved
R/W This bit controls whether to exchange the upper 16-bit
data for the lower 16-bit data if the 32-bit enhanced
bus is enabled.
0: No word swap is executed. The 32-bit data on the
enhanced bus is represented in big endian format.
1: Word swap is executed between the ATAPI
interface and the register/enhanced bus. The 32-bit
data on the enhanced bus is represented in little
endian format.
Word swap in data transfer is enabled only if bit 0 in
the ATAPI control register is set to 1 to initiate DMA
mode. All types of register access are made in
longword units in any mode other than DMA mode.
R/W This bit controls whether to enable the ATAPI
interface.
0: ATAPI interface is disabled.
1: ATAPI interface is enabled.
Note: When this bit is 0, the I/O pins of the ATAPI
interface work as input pins, and the output
pins are in high-impedance state.
Rev. 1.00 Mar. 25, 2008 Page 1317 of 1868
REJ09B0372-0100