SH7205 Datasheet, PDF (369/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
Notes: Before transitioning to or recovering from deep-power-down mode it is necessary to halt
SDRAM access to the affected channels. Consequently, it is not possible to transition to or
recover from deep-power-down mode while programs or DMA operations that access
SDRAM are in progress. Pay attention to the following points when writing programs.
1. Before transitioning to deep-power-down mode, prohibit any DMA channel transfers
that access the SDRAM area of the affected channels.
2. If programs are to be executed during transition to deep-power-down mode, in deep-
power-down mode, or during recovery from deep-power-down mode, design them in
such a way that they will not include operands accessing or fetching (including pre-
fetching) instructions stored in the SDRAM area.
(d) Timing Register Set Values and Access Timing
The correspondence between the SDRAMm timing register (SDmTR) set values and the read and
write access timing is described below.
• Multiple Read Timing Setting Examples
Figures 10.29 to 10.31 show the correspondence between the timing of multiple read operations
involving 4 data units and the set values of the SDRAMm timing register (SDmTR). Table 10.11
lists the SDRAMm timing register (SDmTR) set values for each figure.
Table 10.11 SDITR Set Value Correspondence Table (Multiple Read Timing)
Figure
Figure 10.29
Figure 10.30
Figure 10.31
DRAS
010
000
000
DRCD
00
01
01
DPCG
001
001
001
DCL
010
010
011
Rev. 1.00 Mar. 25, 2008 Page 337 of 1868
REJ09B0372-0100