SH7205 Datasheet, PDF (846/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 Synchronous Serial Communication Unit (SSU)
17.3.8 SS Receive Data Registers 0 to 3 (SSRDR0 to SSRDR3)
SSRDR is an 8-bit register that stores receive data. When 8-bit data length is selected by bits
DATS1 and DATS0 in SSCRL, SSRDR0 is valid. When 16-bit data length is selected, SSRDR0
and SSRDR1 are valid. When 32-bit data length is selected, SSRDR0 to SSRDR3 are valid. The
SSRDR that has not been enabled must not be accessed.
When the SSU has received 1-byte data, it transfers the received serial data from SSTRSR to
SSRDR where it is stored. After this, SSTRSR is ready for reception. Since SSTRSR and SSRDR
function as a double buffer in this way, consecutive receive operations can be performed.
Read SSRDR after confirming that the RDRF bit in SSSR is set to 1.
SSRDR is a read-only register, therefore, cannot be written to by the CPU.
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W
7 to 0
H'00
R
Description
Serial receive data
Table 17.4 Correspondence between DATS Bit Setting and SSRDR
SSRDR
0
1
2
3
00
Valid
Invalid
Invalid
Invalid
DATS[1:0] (SSCRL[1:0])
01
10
11 (Setting Disabled)
Valid
Valid
Invalid
Valid
Valid
Invalid
Invalid
Valid
Invalid
Invalid
Valid
Invalid
Rev. 1.00 Mar. 25, 2008 Page 814 of 1868
REJ09B0372-0100