SH7205 Datasheet, PDF (1600/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 30 Power-Down Modes
30.2.26 Deep Standby Cancel Source Flag Register (DSFR)
DSFR is a 16-bit readable/writable register composed of two types of bits. One is the flags that are
used to confirm which interrupt has canceled deep standby mode. The other is the bit that releases
the retention of pin state after deep standby mode is canceled. When deep standby mode is
canceled by an interrupt (NMI or IRQ) or a manual reset, this register retains the value before the
cancellation although power-on reset exception handling is executed. When deep standby mode is
canceled by a power-on reset, this register is initialized to H'0000.
All flags must be cleared immediately before transition to deep standby mode.
Note: When writing to this register, see section 30.4, Usage Notes.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
IO
KEEP
-
-
-
-
- MRESF NMIF IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W:R/(W)* R
R
R
R
R R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Initial
Bit
Bit Name Value
15
IOKEEP 0
14 to 10 
All 0
9
MRESF 0
R/W
R/(W)*
R
R/(W)*
Description
Pin State Retention
Releases the retention of the pin states after deep standby
mode is canceled.
0: Pin states are not retained.
[Clearing condition]
Writing 0 after reading 1 from this bit
1: Pin states are retained.
[Setting condition]
When deep standby mode is entered
Reserved
These bits are always read as 0. The write value should
always be 0.
MRES Flag
0: No interrupt on MRES pin
1: Interrupt on MRES pin
Rev. 1.00 Mar. 25, 2008 Page 1568 of 1868
REJ09B0372-0100