SH7205 Datasheet, PDF (78/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 2 CPU
2.1.2 Control Registers
The control registers consist of four 32-bit registers: the status register (SR), the global base
register (GBR), the vector base register (VBR), and the jump table base register (TBR).
The status register indicates instruction processing states.
The global base register functions as a base address for the GBR indirect addressing mode to
transfer data to the registers of on-chip peripheral modules.
The vector base register functions as the base address of the exception handling vector area
(including interrupts).
The jump table base register functions as the base address of the function table area.
31
14 13 9 8 7 6 5 4 3 2 1 0
BO CS M Q I[3:0]
S T Status register (SR)
31
GBR
0
Global base register (GBR)
31
VBR
0
Vector base register (VBR)
31
TBR
0
Jump table base register (TBR)
Figure 2.2 Control Registers
(1) Status Register (SR)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
-
BO CS
-
-
-
M
Q
I[3:0]
-
Initial value: 0
0
0
0
0
0
-
-
1
1
1
1
0
R/W: R R/W R/W R
R
R R/W R/W R/W R/W R/W R/W R
2
1
0
-
S
T
0
-
-
R R/W R/W
Rev. 1.00 Mar. 25, 2008 Page 46 of 1868
REJ09B0372-0100