SH7205 Datasheet, PDF (1675/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Module
Name Register Name
Abbreviation
2DG
Pixel format setting register for
graphics (only one bit, SF_FMT, is
synchronized with VSYNC)
GR_PIXLFMT
Operation mode setting register for GR_BLTMODE
blitter
Resize display setting register for GR_RISZSET
graphics
Resize mode select register for
blitter
GR_RISZMOD
Resize delta setting register for
blitter
GR_DELT
Resize horizontal starting phase
register for blitter
GR_HSPHAS
Resize vertical starting phase
register for blitter
GR_VSPHAS
Resize horizontal delta
setting register for output block
(synchronized with VSYNC)
MGR_HDELT
Resize horizontal starting phase
register for output block
(synchronized with VSYNC)
MGR_HPHAS
Logical operation input data register GR_LGDAT
for blitter
Chromakey target color data
register for blitter
GR_DETCOL
Replacement color data register for GR_BRDCOL
blitter blending
Blend 1 control register for blitter GR_BRD1CNT
Mixing mode setting register for
output block (synchronized with
VSYNC)
MGR_MIXMODE
Panel-output horizontal timing
setting register for output block
(synchronized with VSYNC)
MGR_MIXHTMG
Panel-output mixing horizontal valid MGR_MIXHS
area setting register for output block
(synchronized with VSYNC)
Section 32 List of Registers
Number
of Bits Address
32
H'E8000048
Access
Size
16, 32
32
H'E8000050 16, 32
32
H'E8000060 16, 32
32
H'E8000064 16, 32
32
H'E8000068 16, 32
32
H'E800006C 16, 32
32
H'E8000070 16, 32
32
H'E8000074 16, 32
32
H'E8000078 16, 32
32
H'E8000080 16, 32
32
H'E8000084 16, 32
32
H'E8000088 16, 32
32
H'E800008C 16, 32
32
H'E8000098 16, 32
32
H'E80000A0 16, 32
32
H'E80000A4 16, 32
Rev. 1.00 Mar. 25, 2008 Page 1643 of 1868
REJ09B0372-0100