SH7205 Datasheet, PDF (331/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
1
DDPDST 0
R Deep-Power-Down Transition/Recovery Status
When set to 1, this bit indicates that a transition to or
recovery from deep-power-down mode is in progress on
the channel for SDRAM0 or SDRAM1.
0: Transition/recovery not in progress
1: Transition/recovery in progress
0
DMRSST 0
R Mode Register Setting Status
When set to 1, this bit indicates that mode register setting
is in progress for the channel for SDRAM0 or SDRAM1.
0: Mode register setting not in progress
1: Mode register setting in progress
"Transition or recovery in progress" refers to the interval from the point at which the bits listed in
table 10.5 are written to until the corresponding commands are issued.
Table 10.5 List of Status Registers and Bits Requiring Checking
Function
Register Name
Bit Name
Self-refresh
SDRFCNT0
DSFENCm, DSFEN
Initialization sequence
SDIR1
DINIRQCm, DINIRQ
Power-down
SDPWDCNT
DPWDCm, DPWD
Deep-Power-down
SDDPDCNT
DDPDCm, DDPD
Mode register setting
SDmMOD
DMR
Note:
Execution of a self-refresh, a transition to or recovery from power-down or deep-power-
down mode, an initialization sequence, or mode register setting may only be performed
when all status bits are cleared to 0.
Do not rewrite the registers (bits) listed in table 10.5 when any of the status bits (DSRFST,
DINIST, DPWDST, DDPDST, DMRSST) is set to 1.
Rev. 1.00 Mar. 25, 2008 Page 299 of 1868
REJ09B0372-0100