SH7205 Datasheet, PDF (776/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
2

0
R Reserved
This bit is always read as 0. The write value should
always be 0.
1, 0
CKE[1:0] 00
R/W Clock Enable
Select the SCIF clock source and enable or disable
clock output from the SCK pin. Depending on CKE[1:0],
the SCK pin can be used for serial clock output or serial
clock input. If serial clock output is set in clock
synchronous mode, set the C/A bit in SCSMR to 1, and
then set CKE[1:0].
On channels 3 and 4, these bits are reserved and
always read as 0. The write value should always be 0.
• Asynchronous mode
00: Internal clock, SCK pin used for input pin (input
signal is ignored)
01: Internal clock, SCK pin used for clock output
(The output clock frequency is either 16 or 8 times
the bit rate)
10: External clock, SCK pin used for clock input
(The input clock frequency is either 16 or 8 times
the bit rate)
11: Setting prohibited
• Clock synchronous mode
00: Internal clock, SCK pin used for serial clock output
01: Internal clock, SCK pin used for serial clock output
10: External clock, SCK pin used for serial clock input
11: Setting prohibited
Rev. 1.00 Mar. 25, 2008 Page 744 of 1868
REJ09B0372-0100