SH7205 Datasheet, PDF (420/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
Bit
Initial
Bit
Name Value R/W Description
1, 0 DTCM Undefined R/W DMA End Signal Output Control
[1:0]
These bits are used to control the output of the DMA end
signal (DMATCk_N) corresponding to the request source set
in the DCTG bits when the DMA transfer end condition is
detected. When these bits are set to 00, output of the
DMATC_N signal is disabled and the signal is fixed high even
if DMA transfer is completed. When these bits are set to 01,
an active DMATC_N is output from the next cycle after the
start of the read cycle immediately before completion of DMA
transfer. When these bits are set to 10, an active DMATC _N
is output from the next cycle after the start of the write cycle
immediately before completion of DMA transfer.
When these bits are set to 11, the DMATC_N signal goes
active for one clock cycle to output a low pulse at the same
timing as the DMA transfer end interrupt (for details, see
figure 11.6). When selecting USB_0 or USB_1 as the request
source, be sure to set these bit to 10 (see table 11.7).
00: Disables output of the DMA end signal.
01: Outputs the DMA end signal in the last read cycle.
10: Outputs the DMA end signal in the last write cycle.
11: Outputs the DMA end signal after DMA has been
completed.
Note: In the context where indication of transfer request
source number, k, is not necessary, the signal name is
expressed as DMATC_N with k omitted.
Note:
Only write data to this register when the corresponding channel is not engaged in single
operand transfer (the corresponding DASTS bit in the DMA arbitration status register
(DMASTS) is 0) and DMA transfer is disabled (the DMST bit in the DMA activation control
register (DMSCNT) is 0 or the DEN bit in DMA control register B (DMCNTBn) is 0). In other
cases, operation is not guaranteed when data is written to this register.
Table 11.4 shows the counter increment and decrement of DMA source/destination address
registers (for details on the “rotation” addressing mode, see section 11.12, Rotate Function). If
two-dimensional addressing is specified in these bits (SAMOD and DAMOD), the settings of
registers related to two-dimensional addressing (section 11.3.16, DMA Two-Dimensional
Addressing Column Setting Register (DM2DCLMm), and after) become valid. When performing
pipelined transfer to or from external devices and modules that support burst access, make sure to
set the direction bits to select address incrementation (001), rotation (011), or two dimensions
(100).
Rev. 1.00 Mar. 25, 2008 Page 388 of 1868
REJ09B0372-0100