SH7205 Datasheet, PDF (1218/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Bit
Bit Name
6
EOFERR
5
SIGN
4
SACK
3 to 0 
Initial
Value
0
R/W
R/W*¹
0
R/W*¹
0
R/W*¹
Undefined R
Description
PORT0 EOF Error Detection Interrupt Status
This bit is set to 1 when the communication on
PORT0 does not end at the EOF2 timing defined by
USB Specification 2.0.
After detecting an EOFERR interrupt, this module
performs control described below (irrespective of the
setting of the corresponding interrupt enable bit).
Terminate all the pipes in which communications on
PORT0 are currently carried out and perform re-
enumeration of PORT0.
(1) Modifies the UACT bit for PORT0 to 0.
(2) Puts PORT0 into the idle state.
0: EOFERR interrupt not generated
1: EOFERR interrupt generated
Setup Transaction Error Interrupt Status
This bit is set to 1 when ACK response is not
returned from the function device three consecutive
times during a setup transaction issued by this
module. Detailed detection condition is as follows;
(1) Timeout of this module before a response is
received from the function device
(2) An ACK packet was corrupted
(3) Reception of an handshake other than an ACK
(NAK, NTET, or STALL)
0: SIGN interrupt has not occurred
1: SIGN interrupt has occurred
Setup Transaction Normal Response Interrupt Status
This bit is set to 1 when ACK response is received
from the function device during a setup transaction
issued by this module.
0: SACK interrupt has not occurred
1: SACK interrupt has occurred
Reserved
Undefined values are read from these bits. The write
value should always be 0.
Rev. 1.00 Mar. 25, 2008 Page 1186 of 1868
REJ09B0372-0100