SH7205 Datasheet, PDF (417/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
Bit
Initial
Bit
Name Value
R/W Description
23 to 19 
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
18 to 16 SZSEL
[2:0]
Undefined R/W Transfer Data Size Select
These bits are used to set the number of bits transferred in
each single data transfer. A byte (8 bits), word (16 bits), or
longword (32 bits) can be selected as the unit for transfer.
(For details, see section 11.10, Units of Transfer and
Transfer Byte Positions.)
000: Byte (8 bits)
001: Word (16 bits)
010: Longword (32 bits)
011 to 111: Setting prohibited
15

0
R Reserved
This bit is always read as 0. The write value should always
be 0.
14 to 12 SAMOD Undefined R/W Source Address Direction Control
[2:0]
These bits are used to set the source address counting
direction.
If these bits are set to 100 (two-dimensional addressing),
the destination address direction control bits (DAMOD)
cannot be set to 100. Two-dimensional addressing (100)
can be set only in channels 0 to 7. Do not set two-
dimensional addressing in other channels.
000: Fixed
001: Incrementation
010: Decrementation
011: Rotation
100: Two-dimensional addressing
101 to 111: Setting prohibited
11

0
R Reserved
This bit is always read as 0. The write value should always
be 0.
Rev. 1.00 Mar. 25, 2008 Page 385 of 1868
REJ09B0372-0100