SH7205 Datasheet, PDF (419/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
Bit
Initial
Bit
Name Value
R/W Description
2
DACT Undefined R/W Destination DMA-active signal Output Control
This bit is used to control the output of the DMA-active
signal (DMAACTDk_N) for the destination corresponding to
the request source set in the DCTG bits. When this bit is set
to 0, output of the DMAACTD_N signal is disabled and the
signal is fixed high. When this bit is set to 1, a low-level
DMAACTD_N is output (showing that DMA is active) from
the next cycle after the start of the DMAC write cycle. When
an on-chip peripheral module is selected as the DMA
request source, be sure to set this bit to 1 (see table 11.6).
0: Disables output of the DMA-active signal for the
destination
1: Outputs DMA-active signal for the destination during write
access
Note: In the context where indication of transfer request
source number, k, is not necessary, the signal name is
expressed as DMAACTD_N with k omitted.
Rev. 1.00 Mar. 25, 2008 Page 387 of 1868
REJ09B0372-0100