SH7205 Datasheet, PDF (449/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.22 DMA Reload Two-Dimensional Addressing Column Setting Register
(DMR2DCLMm)
DMR2DCLMm is a register used to set the number of data columns to be reloaded to the DMA
two-dimensional addressing column setting register (DM2DCLMm). To enable the reload
function, set the two-dimensional reload function enable bit (2DRLOD) of DMA control register
A (DMCNTAm) to 1. When enabled, it is necessary to set both the DMA two-dimensional
addressing column setting register (DM2DCLMm) and DMA reload two-dimensional addressing
column setting register (DMR2DCLMm).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DRCDN[15:0]
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 16 
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
15 to 0
DRCDN
[15:0]
Undefined R/W DMA Block Data Column Count for Reloading
These bits are used to set the number of data columns in
one block to be reloaded to the DMA two-dimensional
addressing column setting register.
00000000_00000000: 1 data unit
:
11111111_11111111: 65536 data units
Note: Set the number of data units identical to the number
of data units set in the single operand transfer data
count select bits (OPSEL) or a number that is an
integral multiple of the number of data units.
Operation is not guaranteed if different settings are
made.
Rev. 1.00 Mar. 25, 2008 Page 417 of 1868
REJ09B0372-0100