SH7205 Datasheet, PDF (44/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 1 Overview
1.3 Block Diagram
CPU0
SH-2A
CPU core
Floating-point
unit (FPU)
CPU instruction fetch bus
(F bus)
CPU memory access bus
(M bus)
UBCTRG
output
Port
CPU bus
(C bus)
On-chip RAM0
(high-speed)
64 Kbytes
High-speed on-chip
RAM0 access bus
Instruction cache
Operand cache
memory (8 Kbytes) memory (8 Kbytes)
Cache controller
User break
controller
(UBC)
CPU extension bus (I bus)
Bus bridge
BIU0
BIUE
BIU3
BIU2
SH-2A
CPU core
Floating-point
unit (FPU)
CPU1
CPU instruction fetch bus
(F bus)
CPU memory access bus
(M bus)
CPU bus
(C bus)
User break
controller
(UBC)
Instruction cache
Operand cache
memory (8 Kbytes) memory (8 Kbytes)
Cache controller
CPU extension bus (I bus)
On-chip RAM1
(high-speed)
64 Kbytes
High-speed on-chip
RAM1 access bus
Bus bridge
BIU1
Internal CPU0 bus
Internal CPU1 bus
Internal
Internal DMA write bus ^bus
Internal DMA read bus
Peripheral bus 0
controller
Bus state
controller
(BSC)
2D engine
(2DG)
Peripheral bus 3
controller
Peripheral bus 2
controller
Direct memory
access
controller
(DMAC)
USB2.0 host/
function module
(USB)
Peripheral bus 1
controller
Port
Port
External bus I/O
Video I/O
External bus width mode input
Expanded interface
for external bus access
Peripheral bus 3
Peripheral bus 2
Port
DREQ input
DACK output
DACT output
TEND output
Peripheral bus 1
Port
USB bus I/O
USB clock input
(2 ports)
Peripheral bus 0
Clock pulse
generator
(CPG)
I/O ports
AT attachment
packet
interface
(ATAPI)
Interrupt
controller
(INTC)
Multi-function
timer pulse
unit 2
(MTU2)
Compare match
timer
(CMT)
Watchdog
timer
(WDT)
Realtime
clock
(RTC)
Serial
communication
interface with
FIFO (SCIF)
Synchronous
serial
commnication
unit (SSU)
I²C bus
interface 3
(IIC3)
Port
EXTAL input
XTAL output
CKIO I/O
Clock mode input
Port
General I/O
Port
AT attachment
packet
interface I/O
Port
RES input
MRES input
MMI input
IRQ input
PINT input
Port
Timer pulse I/O
Port
WDTOVF output
Port
RTC_X1 input
RTC_X2 output
Port
Serial I/O
Port
Serial I/O
Port
I²C bus I/O
User
debugging
interface
(H-UDI)
Power-down
mode
control
On-chip RAM
(retention)
16 Kbytes
AND/NAND
flash memory
controller
(FLCTL)
D/A converter
(DAC)
A/D converter
(ADC)
Pin function
controller
(PFC)
Controller
area
network
(RCAN-TL1)
Serial sound
interface
with FIFO
(SSIF)
Port
JTAG I/O
Port
Flash memory
I/F I/O
Port
Analog output
Port
Analog input
ADTRG input
Port
CAN bus I/O
Port
Serial I/O
Audio clock input
Figure 1.1 Block Diagram
Rev. 1.00 Mar. 25, 2008 Page 12 of 1868
REJ09B0372-0100