SH7205 Datasheet, PDF (442/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.16 DMA Two-Dimensional Addressing Column Setting Register (DM2DCLMm)
DM2DCLMm is a register used to set the number of data columns in one block in two-
dimensional addressing.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DCDN[15:0]
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value
R/W Description
31 to 16 
All 0
R Reserved
These bits are always read as 0. The write value should
always be 0.
15 to 0 DCDN
[15:0]
Undefined R/W DMA Block Data Column Count
These bits are used to set the number of data columns in
one block.
00000000_00000000: 1 data column
:
11111111_11111111: 65536 data columns
Note: Set the number identical to the number of data units
set in the single operand transfer data count select
bits (OPSEL) or an integral multiple of it. Operation is
not guaranteed if different setting is made.
Rev. 1.00 Mar. 25, 2008 Page 410 of 1868
REJ09B0372-0100